SAM4L Datasheet, PDF (897/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
33.5.2
Interrupt Sources
The DACC interrupt line is connected on one of the internal sources of the NVIC. Using the
DACC interrupt requires the NVIC to be programmed first.
33.6 Functional Description
33.6.1
Digital-to-Analog Conversion
DACC uses the APB clock (CLK_DACC) to perform conversions.
DAC is enabled by writing a one to DACEN in Mode Register (MR). Once enabled, DAC is ready
to operate after a startup time (see electrical characteristics). User must therefore configure
startup time by writing new value in MR.STARTUP, according to APB clcok frequency. Startup
time is therefore (MR.STARTUP+1) * APB clock period.
Once a conversion is started, DAC requires setup time before providing analog result on the
analog pin VOUT (see electrical characteristics).
33.6.2
Conversion FIFO
To provide flexibility and high efficiency, a 4 half-word FIFO is used to handle the data to
convert.
As long as the Transmit Ready bit (TXRDY) in the Interrupt Status Register (ISR) is set to one
the DAC Controller accepts new conversion requests by writing data to the Conversion Data
Register (CDR). Data which cannot be converted immediately are stored in the FIFO.
When the FIFO is full or the DACC is not ready to accept conversion requests, TXRDY is low.
Writing to CDR while TXRDY is low corrupts FIFO data.
User can configure transfer data size. When bit WORD in MR is set to one transfer size is 16 bits
and when WORD is set to one transfer size is 32 bits. In 16 bits transfer size, data to convert is
CDR[9:0] and in 32 bits transfer size, data to convert are CDR[9:0] (first data to convert) and
CDR[25:16] (second data to convert).
33.6.3
Conversion Triggers
Internal trigger mode is selected by writing a zero to Trigger Enable (MR.TRGEN). In internal
trigger mode, conversion starts as soon as DAC is enabled, data is written in the Conversion
Data Register (CDR) and internal trigger event occurs. The internal trigger frequency is configu-
rable through the MR.CLKDIV and must not exceed the maximum frequency allowed by the
DAC. Trigger period is therefore CLKDIV * APB clock period.
External trigger mode is selected by writing a one to MR.TRGEN. The external event source is
configured by writing a zero to Trigger Select (MR.TRGSEL) to select external pin EXT_TRG
and a one to select the peripheral event (from PEVC). With external pin source, DACC waits for
a rising edge to begin conversion. With peripheral event source, DACC waits for event (config-
ured by PEVC) to begin conversion.
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