SAM4L Datasheet, PDF (137/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
11.5.6
11.5.7
Precautions When Entering Power Save Mode.
Modules communicating with external circuits should be disabled before entering a Power Save
Mode that will stop the module operation. This prevents erratic behavior when entering or exiting
Power Save Mode. Refer to the relevant module documentation for recommended actions.
Communication between the synchronous clock domains is disturbed when entering and exiting
Power Save Modes. This means that bus transactions are not allowed between clock domains
affected by the Power Save Mode. The system may hang if the bus clocks are stopped in the
middle of a bus transaction.
When entering a Power Save Mode where AHB clocks are stopped, all AHB masters must be
stopped before entering the Power Save Mode. Also, if there is a chance that any APB write
operations are incomplete, the CPU should perform a read operation from any register on the
APB bus before executing the WFI instruction. This will stall the CPU while waiting for any pend-
ing APB operations to complete.
Note: All these recommendations also apply when changing the power scaling as the system is halted.
Interrupts
The BPM has a number of interrupts:
• AE: Access Error, set if a lock protected register is written without first being unlocked.
• PSOK: Power Scaling configuration OK, set if the requested Power configuration is ready
(regulator mode ready, regulator output voltage as expected).
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