SAM4L Datasheet, PDF (604/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
select (NSS) signal has been raised by the master. The USART can only generate one NSS sig-
nal, and it is possible to use standard I/O lines to address more than one slave.
24.6.15.1
Modes of Operation
The SPI system consists of two data lines and two control lines:
• Master Out Slave In (MOSI): This line supplies the data shifted from master to slave. In
master mode this is connected to TXD, and in slave mode to RXD.
• Master In Slave Out (MISO): This line supplies the data shifted from slave to master. In
master mode this is connected to RXD, and in slave mode to TXD.
• Serial Clock (CLK): This is controlled by the master. One period per bit transmission. In both
modes this is connected to CLK.
• Slave Select (NSS): This control line allows the master to select or deselect a slave. In
master mode this is connected to RTS, and in slave mode to CTS.
Changing SPI mode after initial configuration must be followed by a transceiver software reset in
order to avoid unpredictable behavior.
24.6.15.2
Baud Rate
The baud rate generator operates as described in ”Baud Rate in Synchronous and SPI Mode”
on page 583, with the following requirements:
In SPI Master Mode:
• External clock CLK must not be selected as clock (the Clock Selection field (MR.USCLKS)
must not equal 0x3).
• The USART must drive the CLK pin (MR.CLKO must be one).
• The BRGR.CD field must be at least 0x4.
• If the internal divided clock, CLK_USART/DIV, is selected (MR.USCLKS is one), the value in
BRGR.CD must be even, ensuring a 50:50 duty cycle.
In SPI Slave Mode:
• The frequency of the external clock CLK must be at least four times lower than the system
clock.
24.6.15.3
Data Transfer
Up to nine data bits are successively shifted out on the TXD pin at each edge. There are no
start, parity, or stop bits, and MSB is always sent first. The SPI Clock Polarity (MR.CPOL), and
SPI Clock Phase (MR.CPHA) bits configure CLK by selecting the edges upon which bits are
shifted and sampled, resulting in four non-interoperable protocol modes, see Table 24-16. If
MR.CPOL is zero, the inactive state value of CLK is logic level zero, and if MR.CPOL is one, the
inactive state value of CLK is logic level one. If MR.CPHA is zero, data is changed on the lead-
ing edge of CLK, and captured on the following edge of CLK. If MR.CPHA is one, data is
captured on the leading edge of CLK, and changed on the following edge of CLK. A mas-
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