SAM4L Datasheet, PDF (477/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
20.5.1.3
20.5.1.4
20.5.1.5
To change the clock source for CLK_CNT the following steps must be taken. Note that the WDT
should always be disabled before changing the CLK_CNT source:
1. Write a zero to the Clock Enable bit in the Control Register (CTRL.CEN), leaving the other bits
as they are in the Control Register. This will stop CLK_CNT.
2. Read back CTRL until CTRL.CEN reads zero. The clock has now been stopped.
3. Modify the Clock Source Select bit in CTRL (CTRL.CSSEL) with your new clock selection and
write it to CTRL.
4. Write a one to CTRL.CEN, leaving the other bits as they are in CTRL. This will enable the
clock.
5. Read back CTRL until CTRL.CEN reads one. The clock has now been enabled.
Configuring the WDT
If the MODE bit in the Control Register (CTRL.MODE) is zero, the WDT is in basic mode. The
Time Out Prescale Select (PSEL) field in CTRL (CTRL.PSEL) selects the WDT timeout period:
T_timeout = T_psel = 2^(PSEL+1) / f_{clk_cnt}
Enabling the WDT
To enable the WDT write a one to the Enable bit in the Control Register (CTRL.EN). Due to
internal synchronization, it will take some time for the CTRL.EN bit to read back as one.
Clearing the WDT Counter
The WDT counter must be periodically cleared within T_psel to avoid a watchdog reset to be
issued, see Figure 20-2 on page 478. If the WDT counter is not cleared within T_psel a watchdog
reset will be issued at the end of T_psel, see Figure 20-3 on page 478.
The WDT counter is cleared by writing a one to the Watchdog Clear bit in the Clear Register
(CLR.WDTCLR), at any correct write to CTRL, or when the counter reaches T_timeout and the
device is reset. In basic mode, CLR.WDTCLR can be written at any time when the WDT Counter
Cleared bit in the Status Register (SR.CLEARED) is one. Due to internal synchronization, clear-
ing the WDT counter takes some time. The SR.CLEARED bit is cleared when writing to
CLR.WDTCLR and set when the clearing is done. Any write to the CLR.WDTCLR bit while
SR.CLEARED is zero will not clear the counter.
Writing to the CLR.WDTCLR bit has to be done in a particular sequence to be valid. The Clear
Register must be written twice, first by writing 0x55 to the CLR.KEY field and CLR.WDTCLR set
to one, then by writing 0xAA to CLR.KEY without changing the CLR.WDTCLR bit. Writing to the
Clear Register without the correct sequence has no effect.
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