SAM4L Datasheet, PDF (447/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
• Peripheral Bus clock (PB clock). This is the clock of the peripheral bus the AST is connected
to.
• Generic clock (GCLK). One of the generic clocks is connected to the AST. This clock must be
enabled before use, and remains enabled in sleep modes when the PB clock is active.
• 1kHz clock from the 32kHz oscillator or 32kHz RC Oscillator (CLK_1K). The oscillator must
be enabled before use. Selection between OSC32 and RC32 is done inside the Backup
Power Manager module.
In backup mode only the 32kHz oscillator and the 32kHz RC Oscillator are available. The 1kHz
outputs of those oscillators are also available. Refer to Section 11. ”Backup Power Manager
(BPM)” on page 133 for details.
19.4.3 Interrupts
The AST interrupt request lines are connected to the NVIC. Using the AST interrupts requires
the NVIC to be programmed first.
19.4.4
Peripheral Events
The AST peripheral events are connected via the Peripheral Event System. Refer to Section 31.
”Peripheral Event Controller (PEVC)” on page 839 for details.
19.4.5
Debug Operation
The AST prescaler and counter is not frozen during debug operation when the Core is halted,
unless the bit corresponding to the AST is set in the Peripheral Debug Register (PDBG).
If the AST is configured in a way that requires it to be periodically serviced by the CPU through
interrupts or similar, improper operation or data loss may result during debugging.
19.5 Functional Description
19.5.1
Initialization
Before enabling the AST, the internal AST clock CLK_AST_PRSC must be enabled, following
the procedure specified in Section 19.5.1.1. The Clock Source Select field in the Clock register
(CLOCK.CSSEL) selects the source for this clock. The Clock Enable bit in the Clock register
(CLOCK.CEN) enables the CLK_AST_PRSC.
When CLK_AST_PRSC is enabled, the AST can be enabled by writing a one to the Enable bit in
the Control Register (CR.EN).
19.5.1.1
Enabling and Disabling the AST Clock
The Clock Source Selection field (CLOCK.CSSEL) and the Clock Enable bit (CLOCK.CEN) can-
not be changed simultaneously. Special procedures must be followed for enabling and disabling
the CLK_AST_PRSC and for changing the source for this clock.
To enable CLK_AST_PRSC:
• Write the selected value to CLOCK.CSSEL
• Wait until SR.CLKBUSY reads as zero
• Write a one to CLOCK.CEN, without changing CLOCK.CSSEL
• Wait until SR.CLKBUSY reads as zero
To disable the clock:
• Write a zero to CLOCK.CEN to disable the clock, without changing CLOCK.CSSEL
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