SAM4L Datasheet, PDF (753/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
28.9.1 Control Register
Name:
CR
Access Type:
Read/Write
Offset:
0x00
Reset Value:
0x00000000
31
30
29
28
27
26
25
24
-
-
-
-
-
TENBIT
ADR[9:8]
23
22
21
20
19
18
17
16
ADR[7:0]
15
14
13
12
11
10
9
8
SODR
SOAM
CUP
ACK
PECEN
SMHH
SMDA
-
7
6
SWRST
-
5
4
3
2
1
-
STREN
GCMATCH
SMATCH
SMEN
• TENBIT: Ten Bit Address Match
0: Disables Ten Bit Address Match.
1: Enables Ten Bit Address Match.
• ADR: Slave Address
Slave address used in slave address match. Bits 9:0 are used if in 10-bit mode, bits 6:0 otherwise.
• SODR: Stretch Clock on Data Byte Reception
0: Does not stretch bus clock immediately before ACKing a received data byte.
1: Stretches bus clock immediately before ACKing a received data byte.
• SOAM: Stretch Clock on Address Match
0: Does not stretch bus clock after address match.
1: Stretches bus clock after address match.
• CUP: NBYTES Count Up
0: Causes NBYTES to count down (decrement) per byte transferred.
1: Causes NBYTES to count up (increment) per byte transferred.
• ACK: Slave Receiver Data Phase ACK Value
0: Causes a low value to be returned in the ACK cycle of the data phase in slave receiver mode.
1: Causes a high value to be returned in the ACK cycle of the data phase in slave receiver mode.
• PECEN: Packet Error Checking Enable
0: Disables SMBus PEC (CRC) generation and check.
1: Enables SMBus PEC (CRC) generation and check.
• SMHH: SMBus Host Header
0: Causes the TWIS not to acknowledge the SMBus Host Header.
1: Causes the TWIS to acknowledge the SMBus Host Header.
• SMDA: SMBus Default Address
0: Causes the TWIS not to acknowledge the SMBus Default Address.
1: Causes the TWIS to acknowledge the SMBus Default Address.
• SWRST: Software Reset
This bit will always read as 0.
Writing a zero to this bit has no effect.
42023C–SAM–02/2013
0
SEN
753