SAM4L Datasheet, PDF (64/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
8.7.8
The Debug Port pins assignation is then forced to the EDP function even if they were already
assigned to another module. This allows to connect a debugger at any time without reseting the
device. The connection is non-intrusive meaning that the chip will continue its execution without
being disturbed. The CPU can of course be halted later on by issuing Cortex-M4 OCD features.
SMAP Core Reset Request Source
The EDP has the ability to send a request to the SMAP for a Cortex-M4 Core reset. The proce-
dure to do so is to hold TCK low until RESET_N is released. This mechanism aims at halting the
CPU to prevent it from changing the system configuration while the SMAP is operating.
Figure 8-5. SMAP Core Reset Request Timings Diagram
TCK
RESET_N
re_C s_{o r}e_et_reEsr^Dee_tPq_reu_qe_us_et_{s t}
8.7.9 SWJ-DP
The SMAP can de-assert the core reset request for this operation, refer to Section 8.8.8 ”Cortex-
M4 Core Reset Source” on page 72.
The Cortex-M4 embeds a SWJ-DP Debug port which is the standard CoreSight^™ debug port. It
combines Serial Wire Debug Port (SW-DP), from 2 to 3 pins and JTAG debug Port(JTAG-DP), 5
pins.
By default, the JTAG Debug Port is active. If the host debugger wants to switch to the Serial
Wire Debug Port, it must provide a dedicated JTAG sequence on TMS/SWDIO and
TCK/SWCLK which disables JTAG-DP and enables SW-DP.
When the EDP has been switched to Serial Wire mode, TDO/TRACESWO can be used for trace
(for more information refer to the section below). The asynchronous TRACE output (TRAC-
ESWO) is multiplexed with TDO. So the asynchronous trace can only be used with SW-DP, not
JTAG-DP.
The SWJ-DP provides access to the AHB-AP and SMAP access ports which have the following
APSEL value:
Figure 8-6. Access Ports APSEL
Acces Port (AP)
APSEL
AHB-AP
0
SMAP
1
Refer to the ARM Debug Interface v5.1 Architecture Specification for more details on SWJ-DP.
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