SAM4L Datasheet, PDF (920/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
3. Configure common setup for all sensors (such as CNTCR.TOP, CNTCR.CHARGET,
CNTCR.SPREAD).
4. Write a one to the DMA Enable (CR.DMAEN) and the CR.RUN bit.
Having a separate STATUSSEL and PINSEL allows the user to set up e.g. multiple thresholds
on the same pin. This can be used for having multi-level threshold (proximity and touch), or for
having different signs for the threshold, to capture both decrease and increase in capacitance on
the same sensor.
34.6.8
Spread-Spectrum Operation
In order to reduce Electromagnetic Interference (EMI), a spread-spectrum mode of operation
can be accomplished by adding jitter to the sampling frequency. The spread-spectrum operation
also reduces the probability of periodic interference on the measurements.
Figure 34-6. Counter in Spread-Spectrum Operation
TOP:
0:
Writing a non-zero deviation value to the Spread Spectrum field (CNTCR.SPREAD) will cause
the effective TOP value to alternate in a sawtooth pattern, with 16 different values ranging from
TOP – (16 ⋅ 2^{SPREAD – 1}) to TOP. Figure 34-6 shows in principle how the CATB would vary the
period if the spread spectrum generator varied between 4 different values instead of 16.
34.6.9 Interrupts
The CATB has three interrupt sources:
• SAMPLE - Sample Ready
– New measurement sample ready since last write to ICR.SAMPLE.
• INTCH - In-Touch
– In-touch event detected
• OUTTCH - Out-of-Touch
– Out-of-touch event detected
Each interrupt source has a corresponding bit in the Interrupt Status Register (ISR).
An interrupt request will be generated if the bit in the Interrupt Status Register and the corre-
sponding bit in the Interrupt Mask Register (IMR) are set. The interrupt sources are ORed
together to form one interrupt request. The CATB will generate an interrupt request if at least
one of the corresponding bits in IMR is set. Bits in IMR are set by writing a one to the corre-
sponding bit in the Interrupt Enable Register (IER), and cleared by writing a one to the
corresponding bit in the Interrupt Disable Register (IDR). The interrupt request remains active
until the corresponding bit in ISR is cleared by writing a one to the corresponding bit in the Sta-
tus Clear Register (SCR). Because all the interrupt sources are ORed together, the interrupt
request from the CATB will remain active until all the bits in ISR are cleared.
34.6.10
Peripheral Event Triggered Operation
During normal operation, the CATB performs sensor sampling continuously. In the peripheral-
event-triggered mode of operation, the CATB can receive periodic peripheral events, which trig-
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