SAM4L Datasheet, PDF (337/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
17.5 Product Dependencies
In order to use this module, other parts of the system must be configured correctly, as described
below.
17.5.1 I/O Lines
The USBC pins may be multiplexed with the I/O Controller lines. The user must first configure
the I/O Controller to assign the desired USBC pins to their peripheral functions.
The USB VBUS and ID pin lines should be connected to GPIO pins and the user should monitor
this with software.
17.5.2
Power Management
If the CPU enters a Power Save Mode that disables clocks used by the USBC, the USBC will
stop functioning and resume operation after the system wakes up from Power Save Mode.
17.5.3 Clocks
The USBC has two bus clocks connected: One High Speed Bus clock (CLK_USBC_AHB) and
one Peripheral Bus clock (CLK_USBC_APB). These clocks are generated by the Power Man-
ager. Both clocks are enabled at reset, and can be disabled by the Power Manager. It is
recommended to disable the USBC before disabling the clocks, to avoid freezing the USBC in
an undefined state.
To follow the usb data rate at 12Mbit/s in full-speed mode, the CLK_USBC_AHB clock should be
at minimum 12MHz.
The 48MHz USB clock is generated by a dedicated generic clock from the SCIF module. Before
using the USB, the user must ensure that the USB generic clock (GCLK_USBC) is enabled at
48MHz in the SCIF module.
17.5.4 Interrupts
The USBC interrupt request line is connected to the NVIC. Using the USBC interrupt requires
the NVIC to be programmed first.
The USBC asynchronous interrupts can wake the CPU from any Power Save Mode:
• The ID Transition Interrupt (IDTI)
• The Wakeup Interrupt (WAKEUP)
• The Host Wakeup Interrupt (HWUPI)
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