SAM4L Datasheet, PDF (768/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
28.9.14 HS-mode Timing Register
Name:
HSTR
Access Type:
Read/Write
Offset:
0x34
Reset Value:
0x00000000
31
30
29
28
27
26
25
24
-
-
-
-
-
-
-
-
23
22
21
20
19
18
17
16
HDDAT
15
14
13
12
11
10
9
8
-
-
-
-
-
-
-
-
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
• HDDAT: Data Hold Cycles
Non-prescaled clock cycles for data hold count when the TWIS is in HS-mode. Used to time T_{HD_DAT}. Data is driven HDDAT
cycles after a LOW on TWCK is detected. This timing is used for timing the ACK/NAK bits, and any data bits driven in slave
transmitter mode.
42023C–SAM–02/2013
768