SAM4L Datasheet, PDF (847/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
31.8 User Interface
Table 31-4. PEVC Register Memory Map
Offset
Register
0x000
Channel Status Register
0x004
Channel Enable Register
0x008
Channel Disable Register
0x010
Software Event
0x014
Channel / User Busy
0x020
Trigger Interrupt Mask Enable Register
0x024
Trigger Interrupt Mask Disable Register
0x028
Trigger Interrupt Mask Register
0x030
Trigger Status Register
0x034
Trigger Status Clear Register
0x040
Overrun Interrupt Mask Enable Register
0x044
Overrun Interrupt Mask Disable Register
0x048
Overrun Interrupt Mask Register
0x050
Overrun Status Register
0x054
Overrun Status Clear Register
0x100
Channel Multiplexer 0
0x100
+ i*4
Channel Multiplexer i
0x17C
Channel Multiplexer 31
0x200
Event Shaper 0
0x200
+ j*4
Event Shaper j
0x2FC
Event Shaper 63
0x300
Input Glitch Filter Divider Register
0x3F8
Parameter
0x3FC
Version
Register Name
CHSR
CHER
CHDR
SEV
BUSY
TRIER
TRIDR
TRIMR
TRSR
TRSCR
OVIER
OVIDR
OVIMR
OVSR
OVSCR
CHMX0
CHMXi
CHMX31
EVS0
EVSj
EVS63
IGFDR
PARAMETER
VERSION
Access
Read-only
Write-only
Write-only
Write-only
Read-only
Write-only
Write-only
Read-only
Read-only
Write-only
Write-only
Write-only
Read-only
Read-only
Write-only
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read-only
Read-only
Reset
0x00000000
-
-
-
-⁽¹⁾
-
-
0x00000000
0x00000000
-
-
-
0x00000000
0x00000000
-
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
-⁽¹⁾
-⁽¹⁾
Notes: 1. The reset values for these registers are device specific. Refer to the Module Configuration section at the end of this chapter.
42023C–SAM–02/2013
847