SAM4L Datasheet, PDF (416/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

17.7.3.15 Pipe n Control Register
Register Name:
UPCONn, n in [0..7]
Access Type:
Read-Only
Offset:
0x05C0 + (n * 0x04)
Reset Value:
0x00000000
ATSAM4L4/L2
31
30
29
28
27
26
25
24
-
-
-
-
-
-
-
-
23
22
21
20
19
18
17
16
-
-
-
-
INITBK
INITDTGL
PFREEZE
-
15
14
13
12
11
10
9
8
-
FIFOCON
-
NBUSYBKE
-
RAMACERE
-
-
7
6
5
4
3
2
1
0
-
RXSTALLDE/
CRCERRE
ERRORFIE
NAKEDE
PERRE
TXSTPE
TXOUTE
RXINE
• INITBK: Bank Initialization
This bit is always read as zero.
If the user writes a one to the INITBKC bit, this will set the current bank to Bank0 value for the current pipe.
If the user writes a one to the INITBKS bit, this will set the current bank to Bank1 value for the current pipe.
This may be useful to restore a pipe to manage alternate pipes on the same physical pipe.
• INITTGL: Data Toggle Initialization
This bit is always read as zero.
If the user writes a one to the INITTGLC bit, this will set the Data toggle to Data0 value for the current pipe.
If the user writes a one to the INITTGLS bit, this will set the Data toggle to Data1 value for the current pipe.
This may be useful to restore a pipe to manage alternate pipes on the same physical pipe.
• PFREEZE: Pipe Freeze
This bit is cleared when the PFREEZEC bit is written to one. This will enable the pipe request generation.
This bit is set when the PFREEZES bit is written to one or when the pipe is not configured or when a STALL handshake has
been received on this pipe, or when INRQ In requests have been processed, or after a pipe Enable (UPRST.PEN rising). This
will freeze the pipe requests generation.
If the PFREEZES bit is written to one while a transaction is on going on the USB bus, the transaction will be properly completed
and then the PFREEZE bit will be set. UPSTAn register should be checked to know this last transaction status.
• FIFOCON: FIFO Control
For OUT and SETUP pipes:
This bit is cleared when the FIFOCONC bit is written to one. This will send the FIFO data and switch the bank.
This bit is set when the current bank is free, at the same time than TXOUTI or TXSTPI.
For IN pipes:
This bit is cleared when the FIFOCONC bit is written to one. This will free the current bank and switch to the next bank.
This bit is set when a new IN message is stored in the current bank, at the same time than RXINI.
• NBUSYBKE: Number of Busy Banks Interrupt Enable
This bit is cleared when the NBUSYBKEC bit is written to one. This will disable the Transmitted IN Data interrupt (NBUSYBKE).
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