SAM4L Datasheet, PDF (162/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
12.6.3.11
Power Save Modes
In continuous mode the BOD18/33 will be off during WAIT, RETENTION and BACKUP Power
Save Modes. In sampling mode the BOD18/33 is enabled in all Power Save Modes.
Table 12-2. BOD18/33 in different modes
Mode
Continuous Mode
Possible actions during different
modes
RUN
Reset
Interrupt
SLEEP
Reset
Interrupt
WAIT
OFF
OFF
RETENTION OFF
OFF
BACKUP
OFF
OFF
Sampling Mode
Possible actions during different
Modes
Reset
Interrupt
Reset
Interrupt
Reset
Delayed Interrupt
Reset
Delayed Interrupt
Reset
Delayed Interrupt
12.6.3.12
Flash Fuses
It is not recommended to override the default factory settings, but can be done (after reset) by
writing to the BOD18/33 registers. Refer to the Fuse settings chapter for more details about
BOD18/33 fuses and how to program these fuses.
If the Flash Calibration Done (FCD) bit in the BOD18/33CTRL register is 0 at reset, the flash cal-
ibration will be redone and the BOD18/33CTRL.FCD bit will be set before program execution
starts in the CPU. If BOD18/33CTRL.FCD is one, the BOD18/33 configuration will not be altered
after reset.
12.6.4
Voltage Regulator (VREG)
The embedded voltage regulator can be used to supply all the digital logic in the Core and the
Backup power domains. The VREG features three different modes: normal mode, low power
mode (LP) and Ultra Low Power mode (ULP).
To support Power Scaling and Power Save mode features, the VREG is controlled by the
Backup Power Manager (BPM).
After a reset, the VREG is enabled. If an external voltage is applied on the VDDCORE pin, the
VREG can be disabled by writing a one to the Disable bit of the VREG Configuration register
(VREGCR.DIS).
When the regulator has reached its expected value, the VREGOK bit in the PCLKSR register is
set. An interrupt is generated on a zero-to-one transition of VREGOK.
12.6.4.1
Register Protection
To prevent unexpected writes due to software bugs, write access to the VREGCR register is pro-
tected by a locking mechanism, for details refer to Section 12.7.7 ”Unlock Register” on page
173.
To prevent further modifications by software, the contents of the calibration (VREG.CALIB) and
disable (VREGCR.DIS) fields can be set as read-only by writing a one to the Store Final Value
bit (VREGCR.SFV). Once this bit is set, the contents of VREGCR can not be modified until a
POR18 reset is applied.
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