SAM4L Datasheet, PDF (339/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
17.6.1.2
17.6.1.3
17.6.1.4
Interrupts
One interrupt vector is assigned to the USBC.
See Section 17.6.2.19 and Section 17.6.3.16 for further details about device and host interrupts.
See Section 17.5.4 for asynchronous interrupts.
Frozen clock
When the USB clock is frozen, it is still possible to access the following bits: UIMOD, FRZCLK,
and USBE in the USBCON register, and LS in the UDCON register.
When FRZCLK is set, only the asynchronous interrupts can trigger a USB interrupt (see Section
17.5.4).
Speed control
• Device mode
When the USBC interface is in device mode, the speed selection is done by the UDCON.LS bit,
connecting an internal pull-up resistor to either DP (full-speed mode) or DM (low-speed mode).
The LS bit shall be written before attaching the device, which can be simulated by clearing the
UDCON.DETACH bit.
Figure 17-3. Speed Selection in device mode
VBUS
UDCON.DETACH
UDCON.LS
DP
DM
17.6.1.5
• Host mode
When the USBC interface is in host mode, internal pull-downs are enabled on both DP and DM.
The interface detects the speed of the connected device and reflects this in the Speed Status
field (USBSTA.SPEED).
Data management
Endpoints and pipe buffers can be allocated anywhere in the embedded memory (CPU RAM or
HSB RAM).
See ”RAM management” on page 343.
42023C–SAM–02/2013
339