SAM4L Datasheet, PDF (661/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
26.7.2
Data Transfer
Four combinations of polarity and phase are available for data transfers. The clock polarity is
configured with the Clock Polarity bit in the Chip Select Registers (CSRn.CPOL). The clock
phase is configured with the Clock Phase bit in the CSRn registers (CSRn.NCPHA). These two
bits determine the edges of the clock signal on which data is driven and sampled. Each of the
two bits has two possible states, resulting in four possible combinations that are incompatible
with one another. Thus, a master/slave pair must use the same parameter pair values to com-
municate. If multiple slaves are used and fixed in different configurations, the master must
reconfigure itself each time it needs to communicate with a different slave.
Table 26-2 on page 661 shows the four modes and corresponding parameter settings.
Table 26-2.
SPI modes
SPI Mode
0
1
2
3
CPOL
0
0
1
1
NCPHA
1
0
1
0
Figure 26-3 on page 661 and Figure 26-4 on page 662 show examples of data transfers.
Figure 26-3. SPI Transfer Format (NCPHA = 1, 8 bits per transfer)
SPCK cycle (for reference)
1
2
3
4
5
6
7
8
SPCK
(CPOL = 0)
SPCK
(CPOL = 1)
MOSI
(from master)
MSB
6
5
4
3
2
1
LSB
MISO
(from slave)
MSB
6
5
4
3
2
1
LSB
***
NSS
(to slave)
*** Not Defined, but normaly MSB of previous character received
42023C–SAM–02/2013
661