SAM4L Datasheet, PDF (772/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
29. Inter-IC Sound Controller (IISC)
Rev: 1.0.0.0
29.1 Features
• Compliant with Inter-IC Sound (I²S) bus specification
• Master, slave, and controller modes:
– Slave: data received/transmitted
– Master: data received/transmitted and clocks generated
– Controller: clocks generated
• Individual enable and disable of receiver, transmitter, and clocks
• Configurable clock generator common to receiver and transmitter:
– Suitable for a wide range of sample frequencies (fs), including 32kHz, 44.1kHz, 48kHz,
88.2kHz, 96kHz, and 192kHz
– 16fs to 1024fs Master Clock generated for external oversampling ADCs
• Several data formats supported:
– 32-, 24-, 20-, 18-, 16-, and 8-bit mono or stereo format
– 16- and 8-bit compact stereo format, with left and right samples packed in the same word to
reduce data transfers
• DMA interfaces for receiver and transmitter to reduce processor overhead:
– Either one DMA channel for both audio channels, or
– One DMA channel per audio channel
• Smart holding registers management to avoid audio channels mix after overrun or underrun
29.2 Overview
The Inter-IC Sound Controller (IISC) provides a 5-wire, bidirectional, synchronous, digital audio
link with external audio devices: ISDI, ISDO, IWS, ISCK, and IMCK pins.
This controller is compliant with the Inter-IC Sound (I²S) bus specification.
The IISC consists of a Receiver, a Transmitter, and a common Clock Generator, that can be
enabled separately, to provide Master, Slave, or Controller modes with Receiver, Transmitter, or
both active.
Peripheral DMA channels, separate for the Receiver and for the Transmitter, allow a continuous
high bitrate data transfer without processor intervention to the following:
• Audio CODECs in Master, Slave, or Controller mode
• Stereo DAC or ADC through dedicated I²S serial interface
The IISC can use either a single DMA channel for both audio channels or one DMA channel per
audio channel.
The 8- and 16-bit compact stereo format allows reducing the required DMA bandwidth by trans-
ferring the left and right samples within the same data word.
In Master Mode, the IISC allows outputting a 16 fs to 1024fs Master Clock, in order to provide an
oversampling clock to an external audio codec or digital signal processor (DSP).
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