SAM4L Datasheet, PDF (349/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
• Detailed description
The data is written according to this sequence:
• When the bank is empty, TXINI and FIFOCON are set, which triggers an EPnINT interrupt if
TXINE is one.
• The user acknowledges the interrupt by clearing TXINI.
• The user reads the UESTAX.CURRBK field to see which the current bank is.
• The user writes the data to the current bank, located in RAM as described by its descriptor:
EPn_ADDR_BK0/1.
• The user should write the size of the IN packet into the USB descriptor:
EPn_PCKSIZE_BK0/1.BYTE_COUNT.
• The user allows the controller to send the bank contents and switches to the next bank (if
any) by clearing FIFOCON.
If the endpoint uses several banks, the current one can be written while the previous one is
being read by the host. When the user clears FIFOCON, the next current bank may already be
clear and TXINI is set immediately.
An “Abort” stage can be produced when a zero-length OUT packet is received during an IN
stage of a control or isochronous IN transaction. The Kill IN Bank (KILLBK) bit in UECONn is
used to kill the last written bank. The best way to manage this abort is to apply the algorithm rep-
resented on Figure 17-11 on page 349. See ”Endpoint n Control Register” on page 395 for more
details about the KILLBK bit.
Figure 17-11. Abort Algorithm
Endpoint
Abort
TXINEC = 1
Disable the TXINI interrupt.
NBUSYBK _No
== 0?
Yes
EPRSTn = 1
KILLBKS = 1
Abort Done
KILLBK
Yes
== 1?
No
Abort is based on the fact
that no bank is busy, i.e.,
that nothing has to be sent
Kill the last written bank.
Wait for the end of the
procedure
• Multi packet mode for IN endpoints
In multi packet mode, the user can prepare n USB packets in the bank to be sent on a multiple
IN transaction. The packet sizes will equal UECFGn.EPSIZE unless the AUTO_ZLP option is
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