SAM4L Datasheet, PDF (614/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
– If USART operates in SPI slave mode: At least one SPI underrun error has occurred
since the last RSTSTA.
• TXEMPTY: Transmitter Empty
– There are no characters in neither THR, nor in the transmit shift register.
• TIMEOUT: Receiver Time-out
– There has been a time-out since the last Start Time-out command.
• PARE: Parity Error
– Either at least one parity error has been detected, or the parity bit is a one in
multidrop mode, since the last RSTSTA.
• FRAME: Framing Error
– At least one stop bit has been found as low since the last RSTSTA.
• OVRE: Overrun Error
– At least one overrun error has occurred since the last RSTSTA.
• RXBRK: Break Received/End of Break
– Break received or End of Break detected since the last RSTSTA.
• TXRDY: Transmitter Ready
– There is no character in the THR.
• RXRDY: Receiver Ready
– At least one complete character has been received and RHR has not yet been read.
An interrupt source will set a corresponding bit in the Channel Status Register (CSR). The inter-
rupt sources will generate an interrupt request if the corresponding bit in the Interrupt Mask
Register (IMR) is set. The interrupt sources are ORed together to form one interrupt request.
The USART will generate an interrupt request if at least one of the bits in IMR is set. Bits in IMR
are set by writing a one to the corresponding bit in the Interrupt Enable Register (IER), and
cleared by writing a one to the corresponding bit in the Interrupt Disable Register (IDR). The
interrupt request remains active until the corresponding bit in CSR is cleared. The clearing of the
bits in CSR is described in ”Channel Status Register” on page 625. Because all the interrupt
sources are ORed together, the interrupt request from the USART will remain active until all the
bits in CSR are cleared.
24.6.19 Using the Peripheral DMA Controller
24.6.20
Write Protection Registers
To prevent single software errors from corrupting USART behavior, certain address spaces can
be write-protected by writing the correct Write Protect KEY and writing a one to the Write Protect
Enable bit in the Write Protect Mode Register (WPMR.WPKEY and WPMR.WPEN). Disabling
the write protection is done by writing the correct key to WPMR.WPKEY and a zero to
WPMR.WPEN.
Write attempts to a write-protected register are detected and the Write Protect Violation Status
bit in the Write Protect Status Register (WPSR.WPVS) is set. The Write Protect Violation Source
field (WPSR.WPVSRC) indicates the target register. Writing the correct key to the Write Protect
KEY bit (WPMR.WPKEY) clears WPSR. WPVSRC and WPSR.WPVS.
The protected registers are:
• ”Mode Register” on page 619
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