SAM4L Datasheet, PDF (596/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
24.6.10.10 LIN Response Data Length
The response data length is the number of data fields (bytes), excluding the checksum.
Figure 24-31. Response Data Length
User configuration: 1 - 256 data fields (DLC+1)
Identifier configuration: 2/4/8 data fields
Sync
Break
Sync Identifier
Data
Data
Data
Data Checksum
Field
Field
Field
Field
Field
Field
Field
The response data length can be configured, either by the user, or automatically by bits 4 and 5
in the Identifier (LINIR.IDCHR), in accordance to LIN 1.1. The user selects one of these modes
by writing to the Data Length Mode bit (LINMR.DLM):
• LINMR.DLM=0: the response data length is configured by the user by writing to the 8-bit Data
Length Control field (LINMR.DLC). The response data length equals DLC + 1 bytes.
• LINMR.DLM=1: the response data length is defined by the Identifier (LINIR.IDCHR) bits
according to the table below.
Table 24-14. Response Data Length if DLM = 1
LINIR.IDCHR[5]
LINIR.IDCHR[4]
0
0
0
1
1
0
1
1
Response Data Length [bytes]
2
2
4
8
24.6.10.11
Checksum
The last frame field is the checksum. It is configured by the Checksum Type (LINMR.CHKTYP),
and the Checksum Disable (LINMR.CHKDIS) bits. CSR.TXRDY will not be set after the last THR
data write if enabled. Writing a one to LINMR.CHKDIS will disable the automatic checksum gen-
eration/checking, and the user may send/check this last byte manually, disguised as a normal
data. The checksum is an inverted 8-bit sum with carry, either:
• Over all data bytes, called a classic checksum. This is used for LIN 1.3 compliant slaves, and
automatically managed when CHKDIS=0, and CHKTYP=1.
• Over all data bytes and the protected identifier, called an enhanced checksum. This is used
for LIN 2.0 compliant slaves, and automatically managed when CHKDIS=0, and CHKTYP=0.
24.6.10.12
Frame Slot Mode
A LIN master can be configured to use frame slots with a pre-defined minimum length. This
Frame Slot mode is enabled by default, and is disabled by writing a one to the Frame Slot Mode
Disable bit (LINMR.FSDIS). The Frame Slot mode will not allow CSR.TXRDY to be set after a
frame transfer until the entire frame slot duration has elapsed, in effect preventing the master
from sending a new header. The LIN Transfer Complete bit (CSR.LINTC) will still be set after the
checksum has been sent. An interrupt is generated if the LIN Transfer Complete bit in the Inter-
rupt Mask Register (IMR.LINTC) is set. Writing a one to CR.RSTSTA clears CSR.LINTC.
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