SAM4L Datasheet, PDF (59/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
8.6.2
8.6.3
The FPB unit contains:
• Two literal comparators for matching against literal loads from Code space, and remapping to
a corresponding area in System space.
• Six instruction comparators for matching against instruction fetches from Code space and
remapping to a corresponding area in System space.
• Alternatively, comparators can also be configured to generate a Breakpoint instruction to the
processor core on a match.
DWT (Data Watchpoint and Trace)
The DWT contains four comparators which can be configured to generate the following:
• PC sampling packets at set intervals
• PC or Data watchpoint packets
• Watchpoint event to halt core
The DWT contains counters for the items that follow:
• Clock cycle (CYCCNT)
• Folded instructions
• Load Store Unit (LSU) operations
• Sleep Cycles
• CPI (all instruction cycles except for the first cycle)
• Interrupt overhead
ITM (Instrumentation Trace Macrocell)
The ITM is an application driven trace source that supports printf style debugging to trace Oper-
ating System (OS) and application events, and emits diagnostic system information. The ITM
emits trace information as packets which can be generated by three different sources with sev-
eral priority levels:
• Software trace: This can be done thanks to the printf style debugging. For more information,
refer to Section “How to Configure the ITM:”.
• Hardware trace: The ITM emits packets generated by the DWT.
• Time stamping: Timestamps are emitted relative to packets. The ITM contains a 21-bit
counter to generate the timestamp.
How to Configure the ITM:
The following example describes how to output trace data in asynchronous trace mode.
• Configure the TPIU for asynchronous trace mode (refer to Section “5.4.3. How to Configure
the TPIU”)
• Enable the write accesses into the ITM registers by writing “0xC5ACCE55” into the
Lock Access Register (Address: 0xE0000FB0)
• Write 0x00010015 into the Trace Control Register:
– Enable ITM
– Enable Synchronization packets
– Enable SWO behavior
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