SAM4L Datasheet, PDF (211/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
Timers, communication modules, and other modules connected to external circuitry may require
specific clock frequencies to operate correctly. The SCIF defines a number of generic clocks that
can provide a wide range of accurate clock frequencies.
Each generic clock runs from either clock source listed in the “Generic Clock Sources” table in
the SCIF Module Configuration section. The selected source can optionally be divided by any
even integer up to 512. Each clock can be independently enabled and disabled, and is also
automatically disabled along with peripheral clocks by the Sleep Controller in the Power
Manager.
Figure 13-11. Generic Clock Generation
G e n e ric
C lo ck
Sources
Sleep Controller
f_SRC
OSCSEL
D iv id e r
DIV
0
1
DIVEN
Mask
f_GCLK
Generic Clock
CEN
13.6.8.1
13.6.8.2
13.6.8.3
Enabling a Generic Clock
A generic clock is enabled by writing a one to the Clock Enable bit (CEN) in the Generic Clock
Control Register (GCCTRL). Each generic clock can individually select a clock source by writing
to the Oscillator Select field (OSCSEL). The source clock can optionally be divided by writing a
one to the Divide Enable bit (DIVEN) and the Division Factor field (DIV), resulting in the output
frequency:
f_GCLK
=
---------^f--^S---^R---^C-----------
2(DIV + 1)
where f_SRC is the frequency of the selected source clock, and f_GCLK is the output frequency of the
generic clock.
Disabling a Generic Clock
A generic clock is disabled by writing a zero to CEN or entering a sleep mode that disables the
PB clocks. In either case, the generic clock will be switched off on the first falling edge after the
disabling event, to ensure that no glitches occur. After CEN has been written to zero, the bit will
still read as one until the next falling edge occurs, and the clock is switched off. When writing a
zero to CEN the other bits in GCCTRL should not be changed until CEN reads as zero, to avoid
glitches on the generic clock. The generic clocks will be automatically re-enabled when waking
from sleep.
Changing Clock Frequency
When changing the generic clock frequency by changing OSCSEL or DIV, the clock should be
disabled before being re-enabled with the new clock source or division setting. This prevents
glitches during the transition.
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