SAM4L Datasheet, PDF (257/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

14.3 Block Diagram
PicoCache disabled
Cortex-M4
ATSAM4L4/L2
PicoCache enabled
Cortex-M4
HMATRIX
HMATRIX
PicoCache
2 KB RAM
HRAMC1
256 KB FLASH
PicoCache
2 KB RAM
256 KB FLASH
14.4 Product Dependencies
In order to use this module, other parts of the system must be configured correctly, as described
below.
14.4.1
Power Management
If the CPU enters a Power Save Mode that disables clocks used by the FLASHCALW, the
FLASHCALW will stop functioning and resume operation after the system wakes up from Power
Save Mode.
Write and Erase operation are not allowed when the device in Power Scaling Configuration 1
(BPM.PMCON.PS=1)
14.4.2 Clocks
The FLASHCALW has three bus clocks connected: Two High Speed Bus clock
(CLK_FLASHCALW_AHB and CLK_HRAMC1_AHB) and one Peripheral Bus clock
(CLK_FLASHCALW_APB). These clocks are generated by the Power Manager. Both clocks are
enabled at reset, and can be disabled by writing to the Power Manager. The user has to ensure
that CLK_FLASHCALW_AHB is not turned off before reading the flash or writing the pagebuffer
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