SAM4L Datasheet, PDF (626/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
• CTS/LINBLS: Image of CTS Input, or LIN Bus Line Status (when in LIN mode)
0: CTS or LIN Bus Line is low.
1: CTS or LIN Bus Line is high.
• DCD: Image of DCD Input
0: DCD is low.
1: DCD is high.
• DSR: Image of DSR Input
0: DSR is low.
1: DSR is high.
• RI: Image of RI Input
0: RI is low.
1: RI is high.
• CTSIC: Clear to Send Input Change Flag
0: No change has been detected on the CTS pin since the last CSR read.
1: At least one change has been detected on the CTS pin since the last CSR read.
This bit is cleared when reading CSR.
• DCDIC: Data Carrier Detect Input Change Flag
0: No change has been detected on the DCD pin since the last CSR read.
1: At least one change has been detected on the DCD pin since the last CSR read.
This bit is cleared when reading CSR.
• DSRIC: Data Set Ready Input Change Flag
0: No change has been detected on the DSR pin since the last CSR read.
1: At least one change has been detected on the DSR pin since the last CSR read.
This bit is cleared when reading CSR.
• RIIC: Ring Indicator Input Change Flag
0: No change has been detected on the RI pin since the last CSR read.
1: At least one change has been detected on the RI pin since the last CSR read.
This bit is cleared when reading CSR.
• LINTC: LIN Transfer Completed
0: The USART is either idle or a LIN transfer is ongoing.
1: A LIN transfer has been completed since the last RSTSTA.
This bit is cleared by writing a one to CR.RSTSTA:
• LINID: LIN Identifier
0: No LIN Identifier has been sent or received.
1: A LIN Identifier has been sent (master) or received (slave), since the last RSTSTA.
This bit is cleared by writing a one to CR.RSTSTA:
• NACK: Non Acknowledge
0: No Non Acknowledge has been detected since the last RSTNACK.
1: At least one Non Acknowledge has been detected since the last RSTNACK.
This bit is cleared by writing a one to CR.RSTNACK.
• RXBUFF: Reception Buffer Full
0: The Buffer Full signal from the Peripheral DMA Controller channel is inactive.
1: The Buffer Full signal from the Peripheral DMA Controller channel is active.
• ITER/UNRE: Max Number of Repetitions Reached or SPI Underrun Error
If USART operates in SPI Slave Mode:
UNRE = 0: No SPI underrun error has occurred since the last RSTSTA.
UNRE = 1: At least one SPI underrun error has occurred since the last RSTSTA.
If USART does not operate in SPI Slave Mode, no functionality is associated to UNRE. The bit will behave as ITER if the USART
is in ISO7816 mode:
ITER = 0: Maximum number of repetitions has not been reached since the last RSTSTA.
ITER = 1: Maximum number of repetitions has been reached since the last RSTSTA.
This bit is cleared by writing a one to CR.RSTSTA.
42023C–SAM–02/2013
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