SAM4L Datasheet, PDF (1150/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
42.9.3 SPI Timing
42.9.3.1 Master mode
Figure 42-12. SPI Master Mode with (CPOL= NCPHA= 0) or (CPOL= NCPHA= 1)
SPCK
MISO
SPI0
SPI1
MOSI
SPI2
Figure 42-13. SPI Master Mode with (CPOL= 0 and NCPHA= 1) or (CPOL= 1 and NCPHA= 0)
SPCK
MISO
SPI3
SPI4
MOSI
SPI5
Table 42-59. SPI Timing, Master Mode⁽¹⁾
Symbol
Parameter
SPI0
MISO setup time before SPCK rises
SPI1
MISO hold time after SPCK rises
SPI2
SPCK rising to MOSI delay
SPI3
MISO setup time before SPCK falls
SPI4
MISO hold time after SPCK falls
SPI5
SPCK falling to MOSI delay
Conditions
V_VDDIO from
3.0V to 3.6V,
maximum
external
capacitor =
40 pF
Min
235.8 + (t_{CLK_SPI})/2
24.22
235.8 + (t_{CLK_SPI})/2
24.22
Max
613.10
613.10
Note: 1. These values are based on simulation. These values are not covered by test limits in production.
Maximum SPI Frequency, Master Output
Units
ns
42023C–SAM–02/2013
1150