SAM4L Datasheet, PDF (200/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
13.6.3
Digital Frequency Locked Loop (DFLL) Operation
Rev.: 1.1.0.0
The number of DFLLs is device specific. A specific DFLL is referred to as DFLLx, where x can
be any number from 0 to n, where n refers to the last DFLL instance. Refer to the module config-
uration section for details. The DFLLx is controlled by the corresponding DFLLx registers. DFLLx
is disabled by default, but can be enabled to provide a high-frequency source clock for synchro-
nous and generic clocks.
Features:
• Internal oscillator with no external components
• 20-150MHz output frequency
• Can operate standalone as a high-frequency programmable oscillator in open loop mode
• Can operate as an accurate frequency multiplier against a known frequency in closed loop
mode
• Optional spread-spectrum clock generation
• Very high-frequency multiplication supported - can generate all frequencies from a 32KHz
reference clock
DFLLx can operate in both open loop mode and closed loop mode. In closed loop mode a low-
frequency clock with high accuracy can be used as reference clock to get high accuracy on the
output clock (CLK_DFLLx).
To prevent unexpected writes due to software bugs, write access to the configuration registers is
protected by a locking mechanism. For details refer to Section 13.7.7 ”Unlock Register” on page
222.
Figure 13-3. Block Diagram
C A L IB
4
RANGE
2
COARSE
5
F IN E
8
DFLLx
CLK_DFLLx
CSTEP
FSTEP
5+8
MUL
16
FREQUENCY
TUNER
DFLLxLOCKF
DFLLxLOCKC
DFLLxTRACKOOB
CLK_DFLLx_REF
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