SAM4L Datasheet, PDF (609/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
The Manchester endec uses the same Start Frame Delimiter Selector (MR.ONEBIT) for both
encoder and decoder. If ONEBIT is one, only a Manchester encoded zero will be accepted as a
valid start frame delimiter. If ONEBIT is zero, a data or command sync pattern will be expected.
The Received Sync bit in the Receive Holding Register (RHR.RXSYNH) will be zero if the last
character received is a data sync, and a one if it is a command sync.
Figure 24-48. Preamble Pattern Mismatch
Preamble Mismatch
Manchester coding error
Preamble Mismatch
invalid pattern
Manchester
encoded
data ^Txd
SFD DATA
Preamble Length is set to 8
The receiver samples the RXD line in continuos bit period quarters, making the smallest time
frame in which to assume a bit value three quarters. A start bit is assumed if RXD is zero during
one of these quarters, see Figure 24-49.
Figure 24-49. Asynchronous Start Bit Detection
Sampling
Clock
(16 x)
Manchester
encoded
data ^Txd
Start
Detection
1234
If a valid preamble pattern or start frame delimiter is detected, the receiver continues decoding
with the same synchronization. If a non-valid preamble pattern or a start frame delimiter is
detected, the receiver re-synchronizes at the next valid edge. When a valid start sequence has
been detected, the decoded data is passed to the USART and the user will be notified of any
incoming Manchester encoding violations by the Manchester Error bit (CSR.MANERR). An inter-
rupt request is generated if one of the Manchester Error bits in the Interrupt Mask Register
(IMR.MANE or IMR.MANEA) is set. CSR.MANERR is cleared by writing a one to the Reset Sta-
tus bits in the Control Register (CR.RSTSTA). A violation occurs when there is no transition in
the middle of a bit period. See Figure 24-50 for an illustration of a violation causing the Man-
chester Error bit to be set.
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