SAM4L Datasheet, PDF (31/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
4. Cortex-M4 processor and core peripherals
4.1 Cortex-M4
The Cortex-M4 processor is a high performance 32-bit processor designed for the microcon-
troller market. It offers significant benefits to developers, including:
• outstanding processing performance combined with fast interrupt handling
• enhanced system debug with extensive breakpoint and trace capabilities
• efficient processor core, system and memories
• ultra-low power consumption with integrated sleep modes
• platform security robustness, with integrated memory protection unit (MPU).
Cortex-M4
processor
NVIC
Processor
core
Debug
Access
Port
Memory
protection unit
Serial
Wire
viewer
Flash
patch
Data
watchpoints
Code
interface
Bus matrix
SRAM and
peripheral interface
42023C–SAM–02/2013
The Cortex-M4 processor is built on a high-performance processor core, with a 3-stage pipeline
Harvard architecture, making it ideal for demanding embedded applications. The processor
delivers exceptional power efficiency through an efficient instruction set and extensively opti-
mized design, providing high-end processing hardware including a range of single-cycle and
SIMD multiplication and multiply-with-accumulate capabilities, saturating arithmetic and dedi-
cated hardware division.
To facilitate the design of cost-sensitive devices, the Cortex-M4 processor implements tightly-
coupled system components that reduce processor area while significantly improving interrupt
handling and system debug capabilities. The Cortex-M4 processor implements a version of the
Thumb^® instruction set based on Thumb-2 technology, ensuring high code density and reduced
program memory requirements. The Cortex-M4 instruction set provides the exceptional perfor-
mance expected of a modern 32-bit architecture, with the high code density of 8-bit and 16-bit
microcontrollers.
The Cortex-M4 processor closely integrates a configurable Nested Vectored Interrupt Controller
(NVIC), to deliver industry-leading interrupt performance. The NVIC includes a non-maskable
interrupt (NMI), and provides up to 80 interrupt priority levels. The tight integration of the proces-
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