SAM4L Datasheet, PDF (575/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
Figure 24-3. Transmitter Status
Baud Rate
Clock
TXD
Write
THR
Start
Bit
D0
D1
D2
D3
D4
D5
D6
D7
Parity Stop Start
Bit Bit Bit
D0
D1
D2
D3
D4
D5
D6
D7
Parity Stop
Bit Bit
TXRDY
TXEMPTY
24.6.2.3
Asynchronous Receiver
If the USART is configured in an asynchronous operating mode (MR.SYNC is zero), the receiver
will oversample the RXD input line by either 8 or 16 times the Baud Rate Clock, as selected by
the Oversampling Mode bit (MR.OVER). If the line is zero for half a bit period (four or eight con-
secutive samples, respectively), a start bit will be assumed, and the following 8th or 16th sample
will determine the logical value on the line, resulting in bit values being determined at the middle
of the bit period.
The number of data bits, endianess, parity mode, and stop bits are selected by the same bits
and fields as for the transmitter (MR.CHRL, MR.MODE9, MR.MSBF, MR.PAR, and
MR.NBSTOP). The synchronization mechanism will only consider one stop bit, regardless of the
used protocol, and when the first stop bit has been sampled, the receiver will automatically begin
looking for a new start bit, enabling resynchronization even if there is a protocol mismatch. Fig-
ure 24-4 and Figure 24-5 illustrate start bit detection and character reception in asynchronous
mode.
Figure 24-4. Asynchronous Start Bit Detection
Baud Rate
Clock
Sampling
Clock (x16)
RXD
Sampling
RXD
Sampling
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
D0
Start
Sampling
Detection
123456701234
Start
Rejection
42023C–SAM–02/2013
575