SAM4L Datasheet, PDF (558/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
23.7.14 Glitch Filter Enable Register
Name:
GFER
Access:
Read/Write, Set, Clear, Toggle
Offset:
0x0C0, 0x0C4, 0x0C8, 0x0CC
Reset Value:
-
31
30
29
28
27
26
25
24
P31
P30
P29
P28
P27
P26
P25
P24
23
22
21
20
19
18
17
16
P23
P22
P21
P20
P19
P18
P17
P16
15
14
13
12
11
10
9
8
P15
P14
P13
P12
P11
P10
P9
P8
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
• P0-31: Glitch Filter Enable
0: Glitch filter is disabled for the corresponding pin.
1: Glitch filter is enabled for the corresponding pin.
The value of this register should only be changed when the corresponding bit in IER is zero. Updating GFER while interrupt on
the corresponding pin is enabled can cause an unintentional interrupt to be triggered.
42023C–SAM–02/2013
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