SAM4L Datasheet, PDF (812/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

• RB Compare Effect on TIOB (CMRn.BCPB)
• RC Compare Effect on TIOA (CMRn.ACPC)
• RA Compare Effect on TIOA (CMRn.ACPA)
ATSAM4L4/L2
30.7 2-bit Gray Up/Down Counter for Stepper Motor
Each channel can be independently configured to generate a 2-bit gray count waveform on cor-
responding TIOA, TIOB outputs by means of GCEN bit in SMMRx registers.
Up or Down count can be defined by writing bit DOWN in SMMRx registers.
It is mandatory to configure the channel in WAVE mode in CMR register.
The period of the counters can be programmed on RCx registers.
Figure 30-13. 2-bit Gray Up/Down Counter.
30.8 Write Protection System
In order to bring security to the Timer Counter, a write protection system has been implemented.
The write protection mode prevent the write of BMR, FMR, CMRx, SMMRx, RAx, RBx, RCx reg-
isters. When this mode is enabled and one of the protected registers write, the register write
request canceled.
Due to the nature of the write protection feature, enabling and disabling the write protection
mode requires the use of a security code. Thus when enabling or disabling the write protection
mode the WPKEY field of the WPMR register must be filled with the “TIM” ASCII code (corre-
sponding to 0x54494D) otherwise the register write will be canceled.
42023C–SAM–02/2013
812