SAM4L Datasheet, PDF (1029/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
39.5.1 I/O Lines
The LCDCA pins (SEGx and COMy) are multiplexed with other peripherals. The user must first
configure the I/O Controller to give control of the pins to the LCDCA.
VLCD, BIASL, BIASH, CAPL, CAPH are not multiplexed.
39.5.2
Power Management
This module can control the LCD display while CLK_LCDCA is disabled but stops functioning
when CLK_LCD (32kHz) is disabled.
The power consumption of LCDCA itself can be minimized by:
• using the lowest acceptable frame rate (refer to the LCD glass technical characteristics),
• using the low power waveform (default mode),
•
• configuring the lowest possible contrast value.
39.5.3 Clocks
The APB clock for this module (CLK_LCDCA) is generated by the Power Manager. It can be
enabled or disabled either manually through the user interface of the Power Manager or auto-
matically when the system enters a Power Save Mode that disables the clocks to the peripheral
bus modules. The LCDCA also requires a 32kHz clock (CLK32) that is generated by the Backup
Power Manager. The source of this clock can be either the RC32K or the OSC32K, which must
be enabled using the Backup System Control Interface. When system enters a Power Save
Mode, 32kHz clock can be disabled, see BSCIF and BPM chapter for details.
39.5.4 Interrupts
The LCDCA interrupt request line is connected to the NVIC. Using the interrupt requires the
NVIC to be configured first.
39.5.5 Wake Up
Wake up signal is connected to Power Manager (PM). Using wake up mechanism requires the
PM to enable the corresponding asynchronous wake up source first. Also LCDCA interrupt must
be enabled first.
39.5.6
Debug Operation
When an external debugger forces the CPU into debug mode, the LCDCA continues normal
operation.
39.6 Functional Description
39.6.1
LCD Display
The display memory stores the values of all segments to display. Accessible through APB, it
should be filled before next frame starts.
A start of a new frame triggers the update of the shadow display memory. The content of display
memory is copied into the shadow display memory. A display memory refresh is possible without
affecting data that is sent to the panel. Note that display memory is not initialized at power-up.
When a bit in the display memory is written to one, the corresponding segment will be energized
(ON / opaque), and de-energized (OFF / transparent) when this bit is written to zero.
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