SAM4L Datasheet, PDF (783/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
29.8.2 Mode Register
Name:
MR
Access Type:
Read/Write
Offset:
0x04
Reset Value:
0x00000000
31
30
29
28
27
26
25
24
IWS24
IMCKMODE
IMCKFS
23
22
21
20
19
18
17
16
-
-
-
-
-
-
-
-
15
14
13
12
11
10
9
8
-
TXSAME
TXDMA
TXMONO
RXLOOP
RXDMA
RXMONO
7
6
5
4
3
2
1
0
-
-
-
DATALENGTH
-
MODE
The Mode Register should only be written when the IISC is stopped, in order to avoid unwanted glitches on the IWS, ISCK,
and ISDO outputs. The proper sequence is to write the MR register, then write the CR register to enable the IISC, or to dis-
able the IISC before writing a new value into MR.
• IWS24: IWS TDM Slot Width
0: IWS slot is 32-bit wide for DATALENGTH=18/20/24-bit.
1: IWS slot is 24-bit wide for DATALENGTH=18/20/24-bit.
Refer to Table 29-2, “Slot Length,” on page 776.
• IMCKMODE: Master Clock Mode
0: No Master Clock generated (generic clock is used as ISCK output).
1: Master Clock generated (generic clock is used as IMCK output).
Warning: if IMCK frequency is the same as ISCK, IMCKMODE should not be written as one. Refer to Section 29.6.5 ”Serial
Clock and Word Select Generation” on page 776 and Table 29-2, “Slot Length,” on page 776.
• IMCKFS: Master Clock to fs Ratio
Master Clock frequency is 16*(IMCKFS+1) times the sample rate, i.e. IWS frequency:
Table 29-4. Master Clock to Sample Frequency (fs) Ratio
fs Ratio IMCKFS
16 fs
0
32 fs
1
48 fs
2
64 fs
3
96 fs
5
128 fs
7
192 fs
11
256 fs
15
42023C–SAM–02/2013
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