SAM4L Datasheet, PDF (105/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
10.6.1.3
Clock Ready Flag
There is a slight delay from CPUSEL and PBxSEL being written to the new clock setting taking
effect. During this interval, the Clock Ready bit in the Status Register (SR.CKRDY) will read as
zero. When the clock settings change is completed, the bit will read as one. The Clock Select
registers (CPUSEL, PBxSEL) must not be written to while SR.CKRDY is zero, or the system
may become unstable or hang.
The Clock Ready bit in the Interrupt Status Register (ISR.CKRDY) is set on a SR.CKRDY zero-
to-one transition. If the Clock Ready bit in the Interrupt Mask Register (IMR.CKRDY) is set, an
interrupt request is generated. IMR.CKRDY is set by writing a one to the corresponding bit in the
Interrupt Enable Register (IER.CKRDY).
10.6.2
Peripheral Clock Masking
By default, only the necessary clocks are enabled (see the reset value of the MASK registers). It
is possible to disable or enable the clock for a module in the CPU, or APBx clock domain by
writing the corresponding bit in the Clock Mask register (CPU/HSB/PBx) to zero or one. When a
module is not clocked, it will cease operation, and its registers cannot be read or written. The
module can be re-enabled later by writing the corresponding mask bit to one.
A module may be connected to several clock domains, in which case it will have several mask
bits.
The Maskable Module Clocks table contains a list of implemented maskable clocks.
10.6.2.1
Cautionary Note
Note that clocks should only be switched off if it is certain that the module will not be used.
Switching off the clock for the flash controller will cause a problem if the CPU needs to read from
the flash. Switching off the clock to the Power Manager (PM), which contains the mask registers,
or the corresponding APBx bridge, will make it impossible to write the mask registers again. In
this case, they can only be re-enabled by a system reset.
10.6.2.2
SleepWalking^™
In all power save modes except in BACKUP mode, where the APBx clocks are stopped, the
device can wake partially up if a APBx module asynchronously discovers that it needs its clock.
Only the requested clocks and clock sources needed will be started, and all other clocks will be
masked to zero. E.g. if the main clock source is OSC0, only OSC0 will be started even if other
clock sources were enabled in RUN mode. Also generic clocks can be started in a similar way.
The state where only requested clocks are running is referred to as SleepWalking.
The time spent to start the requested clock is mostly limited by the startup time of the given clock
source. This allows APBx modules to handle incoming requests, while still keeping the power
consumption at a minimum.
When the device is SleepWalking any asynchronous wake up sources can wake up the device
at any time without stopping the requested APBx clock.
All requests to start clocks can be masked by writing to the Peripheral Power Control Register
(PPCR), all requests are enabled at reset.
During SleepWalking the NVIC clock will be running except in BACKUP mode. If an interrupt is
pending when entering SleepWalking, this will wake up the whole device.
42023C–SAM–02/2013
105