SAM4L Datasheet, PDF (203/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
Writing to DFLLxMUL.MUL while in closed loop mode will reset the locks. FINE will be set to half
its maximum value and the full locking sequence will be restarted.
Frequency locking
The locking of the frequency in closed loop mode is divided into two stages. In the COARSE
stage the control logic quickly finds the correct value for DFLLxVAL.COARSE and thereby sets
the output frequency to a value close to the correct frequency. The DFLLx Locked on Coarse
Value bit in PCLKSR (PCLKSR.DFLLxLOCKC) will be set when this is done. An interrupt can be
generated on a zero-to-one transition of PCLKSR.DFLLxLOCKC. In the FINE stage the control
logic tunes the value in DFLLxVAL.FINE so the output frequency will be very close to the desired
frequency. DFLLx Locked on Fine Value bit in PCLKSR (PCLKSR.DFLLxLOCKF) will be set
when this is done. An interrupt can be generated on a zero-to-one transition of PCLKSR.DFLLx-
LOCKF. Figure 13-4 shows the state diagram for the closed loop mode, and how the lock bits
are set.
Figure 13-4. DFLL Closed Loop State Diagram
Measure
DFLLx
1
frequency
DFLLxLOCKC
1
DFLLxLOCKF
1
STABLE
0
Calculate
new
COARSE
value
0
Calculate
new FINE
value
0
Compen-
sate for
drift
42023C–SAM–02/2013
CLK_DFLLx is ready to be used when PCLKSR.DFLLxRDY is set after enabling DFLLx. How-
ever, the accuracy of the output frequency depends on which locks are set.
For lock times, refer to Section 42. ”Electrical Characteristics” on page 1106 chapter.
Frequency error measurement
The ratio between CLK_DFLLx_REF and CLK_DFLLx is measured automatically. The differ-
ence between this ratio and DFLLxMUL is stored in the Multiplication Ratio Difference field in the
DFLLx Ratio Register (DFLLxRATIO.RATIODIFF). The relative error on CLK_DFLLx compared
to the target frequency can be calculated as follows:
ERROR = -^R----^A----^T----^I-^O-----^D----^I--^F----^F-----^â‹---^f--^C---^L---^K---^_--^D----^F--^L---^L---^x--^_---^R---^E---^F-
f_{CLK_DFLLx}
Drift compensation
If the Stable DFLL Frequency bit in DFLLxCONF (DFLLxCONF.STABLE) is zero, the frequency
tuner will automatically compensate for drift in the f_{CLK_DFLLx} without losing either of the locks.
This will result in that DFLLxVAL.FINE can change after every measurement of CLK_DFLLx.
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