SAM4L Datasheet, PDF (873/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
32.6 Functional Description
32.6.1
Construction
The Audio Bitstream DAC is divided into several parts, the user interface, the signal processing
blocks, and the Sigma Delta modulator blocks. See Figure 32-1 on page 871. The user interface
is used to configure the signal processing blocks and to input new data samples to the con-
verter.The signal processing blocks manages volume control, offset control, and upsampling.
The Sigma Delta blocks converts the parallel data to1-bit bitstreams.
32.6.1.1
CIC Interpolation Filter
The interpolation filter in the system is a Cascaded Integrator-Comb (CIC) interpolation filter
which interpolates from F_s to {125, 128, 136}xF_s depending on the control settings. This filter is a
4th order CIC filter, and the basic building blocks of the filter is a comb part and an integrator
part. Since the CIC interpolator has a sinc-function frequency response it is compensated by a
linear phase CIC compensation filter to make the passband response more flat in the range 0-
20kHz, see figure Figure 32-4 on page 877. The frequency response of this type of interpolator
has the first zero at the input sampling frequency. This means that the first repeated specters
created by the upsampling process will not be fully rejected and the output signal will contain sig-
nals from these repeated specters. See Figure 32-6 on page 878.
Since the human ear can not hear frequencies above 20kHz, we should not be affected by this
when the sample rate is above 40kHz, but digital measurement equipment will be affected. This
need to be accounted for when doing measurements on the system to prevent aliasing and
incorrect measurement results.
32.6.1.2
Sigma Delta Modulator
The Sigma Delta modulator is a 3rd order modulator consisting of three differentiators (delta
blocks), three integrators (sigma blocks), and a one bit quantizer. The purpose of the integrators
is to shape the noise, so that the noise is reduced in the audio passband and increased at the
higher frequencies, where it can be filtered out by an analog low-pass filter. To be able to filter
out all the noise at high frequencies the analog low-pass filter must be one order larger than the
Sigma Delta modulator.
32.6.1.3
Recreating the Analog Signal
Since the DAC and DACN outputs from the ABDAC are digital square wave signals, they have
to be passed through a low pass filter to recreate the analog signal. This also means that noise
on the IO voltage will couple through to the analog signal. To remove some of the IO noise the
ABDAC can output a clock signal, CLK, which can be used to resample the DAC and DACN sig-
nals on external Flip-Flops powered by a clean supply.
32.6.2
Initialization
Before enabling the ABDACB the correct configuration must be applied to the Control Register
(CR). Configuring the Alternative Upsampling Ratio bit (CR.ALTUPR), Common Mode Offset
Control bit (CR.CMOC), and the Sampling Frequency field (CR.FS) according to the sampling
rate of the data that is converted and the type of amplifier the outputs are connected to is
required to get the correct behavior of the system. When the correct configuration is applied the
ABDACB can be enabled by writing a one to the Enable bit in the Control Register (CR.EN). The
module is disabled by writing a zero to the Enable bit. The module should be disabled before
entering sleep modes to ensure that the outputs are not left in an undesired state.
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