SAM4L Datasheet, PDF (260/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
14.5.2
Flash Memory Organization
The flash memory is divided into a set of pages. A page is the basic unit addressed when pro-
gramming the flash. A page consists of several words. The pages are grouped into 16 regions of
equal size. _AHBEach of these regions can be locked by a dedicated fuse bit, protecting it from
accidental modification.
• p pages (FLASH_P)
• w bytes in each page and in the page buffer (FLASH_W)
• pw bytes in total (FLASH_PW)
• f general-purpose fuse bits (FLASH_F), used as region lock bits and for other device-specific
purposes
• security fuses
• 1 User page
14.5.3 User Page
The User page is an additional page, outside the regular flash array, that can be used to store
various data, such as calibration data and serial numbers. This page is not erased by regular
chip erase. The User page can only be written and erased by a special set of commands. Read
accesses to the User page are performed just as any other read accesses to the flash. The
address map of the User page is given in Figure 14-2 on page 262.
14.5.4
Read Operations
The on-chip flash memory is typically used for storing instructions to be executed by the CPU.
The CPU will address instructions using the HSB bus, and the FLASHCALW will access the
flash memory and return the addressed 32-bit word.
In systems where the HSB clock period is slower than the access time of the flash memory, the
FLASHCALW can operate in 0 wait state mode, and output one 32-bit word on the bus per clock
cycle. If the clock frequency allows, the user should use 0 wait state mode, because this gives
the highest performance as no stall cycles are encountered.
The FLASHCALW can also operate in systems where the HSB bus clock period is faster than
the access speed of the flash memory. Wait state support and a read granularity of 64 bits
ensure efficiency in such systems.
Performance for systems with high clock frequency is increased since the internal read word
width of the flash memory is 64 bits. When a 32-bit word is to be addressed, the word itself and
also the other word in the same 64-bit location is read.
The user can select the wait states required by writing to the FWS field in the Flash Control Reg-
ister (FCR). It is the responsibility of the user to select a number of wait states compatible with
the clock frequency and timing characteristics of the flash memory.
In 0ws mode, no wait states are encountered on any flash read operations. In 1 ws mode, one
stall cycle is encountered every 64-bit aligned transfer. If the PicoCache is enabled and there is
a hit, then it will service the transfer with no penalty.
The Flash Controller address space is displayed in Figure 14-1. The memory space between
address pw and the User page is reserved, and reading addresses in this space returns an
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