SAM4L Datasheet, PDF (212/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
13.6.8.4
Generic Clock Allocation
The generic clocks are allocated to different functions as shown in the “Generic Clock Allocation”
table in the SCIF Module Configuration section.
13.6.9 Interrupts
The SCIF has the following interrupt sources:
• AE - Access Error:
– A protected SCIF register was accessed without first being correctly unlocked.
• RCFASTLOCKLOST - RCFASTLock Lost
– A to 1 transition on the PCLKSR.RCFASTLOCKLOST bit is detected.
• RCFASTLOCK - RCFAST Lock
– A 0 to 1 transition on the PCLKSR.RCFASTLOCK bit is detected.
• PLLLOCKLOST - PLL Lock Lost
– A to 1 transition on the PCLKSR.PLLLOCKLOST bit is detected.
• PLLLOCK - PLL Lock
– A 0 to 1 transition on the PCLKSR.PLLLOCK bit is detected.
• DFLL0RCS - DFLL Reference Clock Stopped:
– A 0 to 1 transition on the PCLKSR.DFLLRCS bit is detected.
• DFLL0RDY - DFLL Ready:
– A 0 to 1 transition on the PCLKSR.DFLLRDY bit is detected.
• DFLL0LOCKF - DFLL Locked on Fine value:
– A 0 to 1 transition on the PCLKSR.DFLLLOCKF bit is detected.
• DFLL0LOCKC - DFLL Locked on Coarse value:
– A 0 to 1 transition on the PCLKSR.DFLLLOCKC bit is detected.
• OSCRDY - OSCReady:
– A 0 to 1 transition on the PCLKSR.OSCRDY bit is detected.
The interrupt sources will generate an interrupt request if the corresponding bit in the Interrupt
Mask Register is set. The interrupt sources are ORed together to form one interrupt request. The
SCIF will generate an interrupt request if at least one of the bits in the Interrupt Mask Register
(IMR) is set. Bits in IMR are set by writing a one to the corresponding bit in the Interrupt Enable
Register (IER), and cleared by writing a one to the corresponding bit in the Interrupt Disable
Register (IDR). The interrupt request remains active until the corresponding bit in the Interrupt
Status Register (ISR) is cleared by writing a one to the corresponding bit in the Interrupt Clear
Register (ICR). Because all the interrupt sources are ORed together, the interrupt request from
the SCIF will remain active until all the bits in ISR are cleared.
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