SAM4L Datasheet, PDF (991/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
peripheral function. If I/O lines of the ADCIFE are not used by the application, they can be used
for other purposes by the I/O controller.
38.5.2
Power Management
If the CPU enters a power reduction mode that disables clocks used by the ADCIFE, the
ADCIFE will stop functioning and resume operation after the system wakes up from power
reduction mode. Before entering a power reduction mode where the clock to the ADCIFE is
stopped, make sure the Analog-to-Digital Converter cell is put in an inactive state.
If an event is sent to the ADCIFE and the clocks used by the ADCIFE are stopped, the ADCIFE
clock will automatically be requested so that the conversion can be processed.
38.5.3 Clocks
The clock for the ADCIFE bus interface (CLK_ADCIFE) is generated by the Power Manager.
This clock is disabled at reset, and can be enabled/disabled in the Power Manager. It is recom-
mended to disable the ADCIFE before disabling the clock, to avoid freezing the ADCIFE in an
undefined state. Additionally, the ADCIFE depends on a dedicated Generic Clock (GCLK). The
GCLK can be set to a wide range of frequencies and clock sources, and must be enabled by the
System Control Interface (SCIF) before the ADCIFE can be used.
This GCLK can also be muxed with the CLK_ADCIFE clock by writting the Clock Selection bit in
the Configuration Register (CFG.CLKSEL). It is used during the sleep walking mode.
38.5.4
Interrupt Controller
The ADCIFE interrupt line is connected on one of the internal sources of the Interrupt Controller.
Using the ADCIFE requires the Interrupt Controller to be programmed first.
38.5.5
Event System
The event controller provides the ADCIFE a trigger source.
The ADCIFE also behaves as an event source:
• Event on an end of conversion (Figure 38-1 adcife_pevc_eoc signal)
• Event on a window monitor trigger (Figure 38-1 adcife_pevc_wm signal)
To operate correctly, the event source period should not exceed the ADC conversion time plus
the startup time if needed.
Refer to the Peripheral Event System chapter for details.
38.6 Section 42. ”Electrical Characteristics” on page 1106Functional Description
38.6.1
Initializing the ADCIFE
To initialize the module the user first needs to configure the ADCIFE clocks (refer to Section
38.5.3). Then he needs to wait for the STARTUP time (Refer to Section 38.6.7) (If necessary).
Then he can write a one to the Enable (EN) bit in the Control Register (CR). The user must
check that ADCIFE has started correctly, firstly by checking that the Enable bit (EN) located in
the Status Register (SR) is set. The Bandgap Buffer Request bit in the Control register
(CR.BGREQEN) and the Reference Buffer Enable in the Control register (CR.REFBUFEN) must
be set. If the reference buffer of the ADC cell is enabled and ready for use, SR.EN can tell if the
ADCIFE is ready for operation since startup-time will be performed only when a sequencer trig-
ger event occurs if necessary.
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