SAM4L Datasheet, PDF (690/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

26.8.12 Chip Select Register 3
Name:
CSR3
Access Type:
Read/Write
Offset:
0x3C
Reset Value:
0x00000000
ATSAM4L4/L2
31
30
29
28
27
26
25
24
DLYBCT
23
22
21
20
19
18
17
16
DLYBS
15
14
13
12
11
10
9
8
SCBR
7
6
5
4
3
2
1
0
BITS
CSAAT
CSNAAT
NCPHA
CPOL
• DLYBCT: Delay Between Consecutive Transfers
This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select. The
delay is always inserted after each transfer and before removing the chip select if needed.
When DLYBCT equals zero, no delay between consecutive transfers is inserted and the clock keeps its duty cycle over the
character transfers.
Otherwise, the following equation determines the delay:
Delay Between Consecutive Transfers = ³----²-----^×----^D-----^L----^Y----^B----^C----^T--
CLKSPI
• DLYBS: Delay Before SPCK
This field defines the delay from NPCS valid to the first valid SPCK transition.
When DLYBS equals zero, the NPCS valid to SPCK transition is 1/2 the SPCK clock period.
Otherwise, the following equations determine the delay:
Delay Before SPCK = --^D-----^L---^Y----^B----^S---
CLKSPI
• SCBR: Serial Clock Baud Rate
In Master Mode, the SPI Interface uses a modulus counter to derive the SPCK baud rate from the CLK_SPI. The Baud rate is
selected by writing a value from 1 to 255 in the SCBR field. The following equations determine the SPCK baud rate:
SPCK Baudrate = -^C----^L----^K----^S---^P-----^I
SCBR
Writing the SCBR field to zero is forbidden. Triggering a transfer while SCBR is zero can lead to unpredictable results.
At reset, SCBR is zero and the user has to write it to a valid value before performing the first transfer.
If a clock divider (SCBRn) field is set to one and the other SCBR fields differ from one, access on CSn is correct but no correct
access will be possible on other CS.
42023C–SAM–02/2013
690