SAM4L Datasheet, PDF (705/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
27.8.2.2
period of the TWCK signal. The TWIM enables its current-source pull-up circuit again when all
devices have released the TWCK line and the line reaches a HIGH level.
Clock Generation
When the TWIM is in F/S-mode, theClock Waveform Generator Register (CWGR) is used to
control the waveform of the TWCK clock. CWGR must be written so that the desired TWI bus
timings are generated. CWGR describes bus timings as a function of cycles of a prescaled
clock. The clock prescaling can be selected through the Clock Prescaler field in CWGR
(CWGR.EXP).
f_PRESCALER
=
f_{--C----L--K---_---T---W----I--M--}
2^{(EXP + 1)}
CWGR has the following fields:
LOW: Prescaled clock cycles in clock low count. Used to time T_LOW and T_BUF.
HIGH: Prescaled clock cycles in clock high count. Used to time T_HIGH.
STASTO: Prescaled clock cycles in clock high count. Used to time T_{HD_STA}, T_{SU_STA}, T_{SU_STO}.
DATA: Prescaled clock cycles for data setup and hold count. Used to time T_{HD_DAT}, T_{SU_DAT}.
EXP: Specifies the clock prescaler setting.
Note that the total clock low time generated is the sum of T_{HD_DAT} + T_{SU_DAT} + T_LOW.
Any slave or other bus master taking part in the transfer may extend the TWCK low period at any
time.
The TWIM hardware monitors the state of the TWCK line as required by the I²C specification.
The clock generation counters are started when a high/low level is detected on the TWCK line,
not when the TWIM hardware releases/drives the TWCK line. This means that the CWGR set-
tings alone do not determine the TWCK frequency. The CWGR settings determine the clock low
time and the clock high time, but the TWCK rise and fall times are determined by the external cir-
cuitry (capacitive load, etc.).
When the TWIM is in HS-mode, the HS-mode Clock Waveform Generator Register (HSCWGR),
instead of CWGR, is used to generate the TWCK signal. HSCWGR has the same fields as
CWGR serving the same purposes.
42023C–SAM–02/2013
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