SAM4L Datasheet, PDF (362/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
Figure 17-21. Example of an OUT pipe with two data banks and a bank switching delay
TXOUTI
SW
OUT
DATA
(bank 0)
SW
ACK
OUT
HW
SW
DATA
(bank 1)
ACK
FIFOCON
write data to CPU _SW
BANK 0
write data to CPU _SW
BANK 1
write data to CPU
BANK0
• Multi packet mode for OUT pipes
See section ”Multi packet mode for IN endpoints” on page 349 and just replace IN endpoints with
OUT pipe.
17.6.3.13
Alternate pipe
The user has the possibility to run sequentially several logical pipes on the same physical pipe.
Before switching pipe, the user should save the pipe context (UPCFGn, UPCONn, UPSTAn,
and the pipe descriptor table).
After switching pipe, the user should restore the pipe context, current bank number, and the cur-
rent data toggle by using the UPCONn.INITDTGL and UPCONn.INITBK bits.
17.6.3.14
Data flow error
This error exists only for isochronous and interrupt pipes for both IN and OUT directions. It sets
the Errorflow Interrupt (ERRORFI) bit in UPSTAn, which triggers an PnINT interrupt if the Error-
flow Interrupt Enable (ERRORFE) bit is one. The user can check the
Pn_CTR_STA_BK0/1.UNDERF and OVERF bits in the pipe descriptor to see which current
bank has been affected.
• An overflow can occur during an OUT stage if the host attempts to send data from an empty
bank. The pipe descriptor Pn_CTR_STA_BK0/1.OVERF points out the bank from which the
OUT data should have originated. If the UPSTAn.ERRORFI bit is cleared and a new
transaction is successful, the Pn_CTR_STA_BK0/1.OVERF bit will be cleared.
• An underflow can occur during an IN stage if the device tries to send a packet while the bank
is full. Typically this occurs when a CPU is not fast enough. The packet data is not written to
the bank and is lost. The pipe descriptor Pn_CTR_STA_BK0/1.UNDERF points out which
bank the OUT data was destined to. If UPSTAn.UNDERFI is zero and a new successful
transaction occurs, Pn_CTR_STA_BK0/1.UNDERF will be cleared.
17.6.3.15
CRC error
This error exists only for isochronous IN pipes. It sets the CRC Error Interrupt bit (CRCERRI),
which triggers a PnINT interrupt if the CRC Error Interrupt Enable bit (UPCONn.CRCERRE) is
one.
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