SAM4L Datasheet, PDF (109/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
10.7 User Interface
Table 10-3. PM Register Memory Map
Offset
Register
0x000
Main Clock Control
0x004
CPU Clock Select
0x00C
PBA Clock Select
0x010
PBB Clock Select
0x014
PBC Clock Select
0x018
PBD Clock Select
0x020
CPU Mask
0x024
HSB Mask
0x028
PBA Mask
0x02C
PBB Mask
0x030
PBC Mask
0x034
PBD Mask
0x040
PBA Divided Mask
0x054
Clock Failure Detector Control
0x058
Unlock Register
0x0C0
Interrupt Enable Register
0x0C4
Interrupt Disable Register
0x0C8
Interrupt Mask Register
0x0CC
Interrupt Status Register
0x0D0
Interrupt Clear Register
0x0D4
Status Register
0x160
Peripheral Power Control Register
0x180
Reset Cause Register
0x184
Wake Cause Register
0x188
Asynchronous Wake Enable
0x18C
Protection Control Register
0x194
Fast Sleep Register
0x3F8
Configuration Register
0x3FC
Version Register
Register Name
MCCTRL
CPUSEL
PBASEL
PBBSEL
PBCSEL
PBDSEL
CPUMASK
HSBMASK
PBAMASK
PBBMASK
PBCMASK
PBDMASK
PBADIVMASK
CFDCTRL
UNLOCK
IER
IDR
IMR
ISR
ICR
SR
PPCR
RCAUSE
WCAUSE
AWEN
PROTCTRL
FASTSLEEP
CONFIG
VERSION
Access
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Write-only
Write-only
Write-only
Read-only
Read-only
Write-only
Read-only
Read/Write
Read-only
Read-only
Read/Write
Read/Write
Read/Write
Read-only
Read-only
Reset
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000001
0x000001E2
0x00000000
0x00000001
0x0000001F
0x0000003F
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x000001FE
-⁽²⁾
-⁽³⁾
0x00000000
0x00000000
0x00000000
0x0000000F
-⁽¹⁾
Note:
1. The reset value is device specific. Refer to the Module Configuration section at the end of this chapter.
2. Latest Reset Source.
3. Latest Wake Source.
42023C–SAM–02/2013
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