SAM4L Datasheet, PDF (1035/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
Each frame counter is enabled by writing a one to Frame Counter x Enable (CR.FCxEN) and
disabled by writing a one to Frame Counter x Disable (CR.FCxDIS). Frame counter must be dis-
abled (SR.FCxS=0) before the update of its associated TIM.FCx value.
39.6.6 CPU Display Memory Access
39.6.6.1
Direct Access
CPU can access display memory in direct access by writing to Data Register Low x (DRLx) and
Data Register High x (DRHx). Read-modify-write operation is then required to update few bits.
To modify a segment defined by SEGx / COMy, select register R and bit B:
R = (y << 6 + x) >> 5
B = x & 0x1F
Where R is the register index in the list {DRL0, DRH0, DRL1, DRH1, DRL2, DRH2, DRL3,
DRH3} and B is the bit position in this register.
39.6.6.2
Indirect Access
CPU can also update up to 8 bits in display memory in indirect access by writing to Indirect
Access Data Register (IADR). It allows to modify 1 up to 8 bits in a single operation without mod-
ifying masked bits in display memory (no read-modify-write operation). This register requires:
• DATA[7:0], each bit represents the state of a segment,
• DMASK[7:0], each bit is a mask for DATA field. When DMASK[x]=1, DATA[x] is not written to
display memory,
• OFF[4:0], byte offset in display memory (see Figure 39-3 on page 1030).
To modify a segment defined by SEGx / COMy, write byte at offset OFF, bit B:
OFF = (5(y << 3) + x) >> 3
B = x & 0x7
39.6.7
Locking Shadow Display Memory
Writing a one to LOCK bit, in Configuration register (CFG), freezes the shadow display memory
update. Then if the display memory is modified, the display remains unchanged. When this bit is
cleared, the shadow display memory is updated when a new frame starts.
39.6.8 Blinking Modes
39.6.8.1
Software Blinking
Writing bit BLANK in CFG register to one turns OFF all LCD segments at the next frame. If
BLANK=0 the content of the display memory is output on the LCD. The blink frequency is then
software dependant. To avoid unexpected intermediate display, blank command should be writ-
ten after the end of the frame (SR.FC0R=1).
LCD controller must be running (frames are generated) to blink segments.
39.6.8.2
Hardware Blinking
To blink all segments on LCD panel, write a zero to Blink Mode (MODE) in Blink Configuration
Register (BCFG). Write a one to MODE to blink selected segments.
42023C–SAM–02/2013
1035