SAM4L Datasheet, PDF (361/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
TXOUTI shall be cleared by software to acknowledge the interrupt. This is done by writing a one
to the Transmitted OUT Data Interrupt Clear bit (UPCONnCLR.TXOUTIC), which does not affect
the pipe FIFO.
The user writes the OUT data to the bank referenced to by the PEPn descriptor and allows the
USBC to send the data by writing a one to the FIFO Control Clear (UPCONnCLR.FIFOCONC)
bit. This will also cause a switch to the next bank if the OUT pipe is composed of multiple banks.
The TXOUTI and FIFOCON bits will be updated accordingly
TXOUTI shall always be cleared before clearing FIFOCON to avoid missing an TXOUTI event.
Note that if the user decides to switch to the Suspend state (by writing a zero to UHCON.SOFE)
while a bank is ready to be sent, the USBC automatically exits this state and sends the data.
Figure 17-19. Example of an OUT pipe with one data bank
OUT
DATA
(bank 0)
ACK
OUT
TXOUTI
SW
HW
SW
FIFOCON
write data to CPU
SW
BANK 0
write data to CPU
SW
BANK 0
Figure 17-20. Example of an OUT pipe with two data banks and no bank switching delay
TXOUTI
SW
OUT
DATA
(bank 0)
ACK
HW
SW
OUT
DATA
(bank 1)
ACK
SW
FIFOCON
write data to CPU _SW
BANK 0
write data to CPU
BANK 1
SW
write data to CPU
BANK0
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