SAM4L Datasheet, PDF (890/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
32.7.9 Status Register
Name:
SR
Access Type:
Read-only
Offset:
0x20
Reset Value:
0x00000000
31
30
29
28
27
26
25
24
-
-
-
-
-
-
-
-
23
22
21
20
19
18
17
16
-
-
-
-
-
-
-
-
15
14
13
12
11
10
9
8
-
-
-
-
-
-
-
-
7
6
5
4
3
2
1
0
-
-
-
-
-
TXUR
TXRDY
BUSY
• TXUR: Transmit Underrun
This bit is cleared when no underrun has occurred since the last time this bit was cleared (by reset or by writing to SCR).
This bit is set when at least one underrun has occurred since the last time this bit was cleared (by reset or by writing to SCR).
• TXRDY: Transmit Ready
This bit is cleared when the ABDACB is not ready to receive a new data in SDR.
This bit is set when the ABDACB is ready to receive a new data in SDR.
• BUSY: ABDACB Busy
This bit is set when the ABDACB is busy doing a data transfer between clock domains. CR, SDR0, and SDR1 can not be written
during this time.
42023C–SAM–02/2013
890