SAM4L Datasheet, PDF (313/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
16.3 Block Diagram
Figure 16-1. PDCA Block Diagram
Memory
HSB to PB
HSB
Bridge
HSB
High Speed
Bus Matrix
Interrupt
Controller
HSB
Peripheral DMA
Controller
(PDCA)
IRQ
Peripheral
0
Peripheral
1
Peripheral
2
Peripheral
(n-1)
Handshake Interfaces
16.4 Product Dependencies
In order to use this module, other parts of the system must be configured correctly, as described
below.
16.4.1
Power Management
If the CPU enters a sleep mode that disables the PDCA clocks, the PDCA will stop functioning
and resume operation after the system wakes up from sleep mode.
16.4.2 Clocks
The PDCA has two bus clocks connected: One High Speed Bus clock (CLK_PDCA_HSB) and
one Peripheral Bus clock (CLK_PDCA_PB). These clocks are generated by the Power Man-
ager. The status of both clocks at reset can be known in the Power Manager section. It is
recommended to disable the PDCA before disabling the clocks, to avoid freezing the PDCA in
an undefined state.
16.4.3 Interrupts
The PDCA interrupt request lines are connected to the NVIC. Using the PDCA interrupts
requires the NVIC to be programmed first.
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