SAM4L Datasheet, PDF (266/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
14.5.9 PicoCache Description
14.5.9.1
Overview
The PicoCache is an unified direct mapped cache controller. It integrates a controller, a tag
directory, a data memory, a metadata memory and a configuration interface. When it is not acti-
vated, the cache memory is accessible as a supplementary RAM connected on the bus matrix.
Note that for security reasons, this memory is cleared by a chip erase operation.
14.5.9.2
Cache Operation
On reset, the cache controller data entries are all invalidated and the cache is disabled. The
cache is transparent to processor operations making flash access timings predicatable. The
cache controller is activated through the use of its configuration registers. Use the following
sequence to enable the cache controller
1. Verify that the cache controller is disabled, reading the value of the CSTS (cache sta-
tus) field of the SR register.
2. Enable the cache controller writing one to CEN (cache enable) field of the CTRL
register.
14.5.9.3
Cache Invalidate By Line Operation
When an invalidate by line command is issued the cache controller reset the valid bit information
of the decoded cache line. As the line is no longer valid the replacement counter points to that
line.
Use the following sequence to invalidate one line of cache:
1. Disable the cache controller writing 0 to the CEN field of the CTRL register.
2. Check CSTS field of the SR to verify that the cache is successfully disabled.
3. Perform an invalidate by line writing the field index in the MAINT1 register.
4. Enable the cache controller writing 1 to the CEN field of the CTRL register.
14.5.9.4
Cache Invalidate All Operation
Use the following sequence to invalidate all cache entries:
1. Write 1 to the INVALL field of the MAINT0 register.
14.5.9.5
Cache Performance Monitoring
This module includes a programmable monitor 32-bit counter. The monitor can be configured to
count the number of clock cycles, the number of data hit or the number of instruction hit.
Use the following sequence to activate the counter
1. Configure the monitor counter writing the MODE field of the CFG register.
2. Enable the counter writing one to the MENABLE field of the MEN register.
3. If required reset the counter, writing one to the SWRST field of the MCTRL register.
4. Check the value of the monitor counter, reading EVENT_CNT field of the SR
14.5.10
Accessing the PicoCache Memory Block As a Regular Memory On the System Bus
This is only possible when the PicoCache is disabled. In case of an access in this memory while
the PicoCache is active, the memory slave will return an error response which will result in a
42023C–SAM–02/2013
266