SAM4L Datasheet, PDF (1083/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
41.5
Functional Description
Once configured (Mode Register, MR) and enabled by writing a one to MR.ENABLE, the CRC
engine performs a checksum computation from memory data. CRC computation is performed
from LSB to MSB bit. Three different polynomials (CCIT802.3, CASTAGNOLI, CCIT16) can be
configured in MR.PTYPE.
CRCCU uses its own DMA mechanism to read memory area (Flash or RAM area). DMA uses a
descriptor located in memory area. Descriptor location is defined by the Descriptor Base
Address Register (DSCR).
Figure 41-2. CRCCU Descriptor
Memory area
DSCR
DSCR+0x04
DSCR+0x10
ADDR
CTRL
reserved
reserved
CRC
42023C–SAM–02/2013
data1
data2
data3
...
Once enabled (DMAEN register), DMA reads descriptor to get instructions:
• ADDR returns the address of memory area to compute,
• CTRL.TRWIDTH indicates the transfer size (byte, halfword or word),
• CTRL.BTSIZE indicates the buffer size,
• CTRL.IEN enables the transfer-complete interrupt.
Then reads data located at ADDR and CRC engine computes the checksum. The CRC result is
available in Status Register (SR). BTSIZE is automatically decremented after each read. When
BTSIZE is zero, DMA is stopped and the status bit DMASR in DMASR register is set to zero.
If MR.COMPARE is set to one, CRC register in descriptor is compared with the last CRC com-
puted. If a mismatch occurs, the error bit ERRISR in ISR register is set to one and interrupt is
generated (if not masked, see IER/IDR/IMR register).
CRCCU makes single access (TRWIDTH size) to memory in order to limit the bandwidth usage.
The field DIVIDER in MR can be used to lower the bandwidth by dividing the frequency of single
accesses. The transfer request frequency is then divided by 2^(DIVIDER+1).
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