SAM4L Datasheet, PDF(379/1185 Page) ATMEL Corporation – ATSAM ARM-based Flash MCU

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SAM4L Datasheet, PDF (379/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

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17.7.2.2 Device Global Interrupt Register

Register Name:

UDINT

Access Type:

Read-Only

Offset:

0x0004

Reset Value:

0x00000000

ATSAM4L4/L2

31

30

29

28

27

26

25

24

-

-

-

-

-

-

-

-

23

22

21

20

19

18

17

16

-

-

-

EP8INT(1)

EP7INT(1)

EP6INT(1)

EP5INT(1)

EP4INT(1)

15

14

13

12

11

10

9

8

EP3INT(1)

EP2INT(1)

EP1INT(1)

EP0INT

-

-

-

-

7

6

5

4

3

2

-

UPRSM

EORSM

WAKEUP

EORST

SOF

1

0

-

SUSP

Note: 1. EPnINT bits are within the range from EP0INT to EP7INT.

â¢ EPnINT: Endpoint n Interrupt

This bit is cleared when the interrupt source is serviced.

This bit is set when an interrupt is triggered by the endpoint n (UESTAn, UECONn). This triggers a USB interrupt if EPnINTE is

one.

â¢ UPRSM: Upstream Resume Interrupt

This bit is cleared when the UDINTCLR.UPRSMC bit is written to one to acknowledge the interrupt (USB clock inputs must be

enabled before).

This bit is set when the USBC sends a resume signal called âUpstream Resumeâ. This triggers a USB interrupt if UPRSME is

one.

â¢ EORSM: End of Resume Interrupt

This bit is cleared when the UDINTCLR.EORSMC bit is written to one to acknowledge the interrupt.

This bit is set when the USBC detects a valid âEnd of Resumeâ signal initiated by the host. This triggers a USB interrupt if

EORSME is one.

â¢ WAKEUP: Wakeup Interrupt

This bit is cleared when the UDINTCLR.WAKEUPC bit is written to one to acknowledge the interrupt (USB clock inputs must be

enabled before).

This bit is set when the USBC is reactivated by a filtered non-idle signal from the lines (not by an upstream resume). This

triggers an interrupt if WAKEUPE is one.

This interrupt is generated even if the clock is frozen by the FRZCLK bit.

â¢ EORST: End of Reset Interrupt

This bit is cleared when the UDINTCLR.EORSTC bit is written to one to acknowledge the interrupt.

This bit is set when a USB âEnd of Resetâ has been detected. This triggers a USB interrupt if EORSTE is one.

â¢ SOF: Start of Frame Interrupt

This bit is cleared when the UDINTCLR.SOFC bit is written to one to acknowledge the interrupt.

This bit is set when either a USB âStart of Frameâ PID (SOF) or a Low-speed keep-alive has been detected (every 1 ms). This

triggers a USB interrupt if SOFE is one. The FNUM field is updated.

42023CâSAMâ02/2013

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