SAM4L Datasheet, PDF (347/1185 Pages) ATMEL Corporation – ATSAM ARM-based Flash MCU

ATSAM4L4/L2
Figure 17-7. Control Write
SETUP
USB Bus SETUP
RXSTPI
HW
SW
RXOUTI
TXINI
OUT
HW
DATA
OUT
SW
HW
STATUS
IN
IN
NAK
SW
SW
• Control read
Figure 17-8 on page 347 shows a control read transaction. The USBC has to manage the simul-
taneous write requests from the CPU and USB host.
Figure 17-8. Control Read
USB Bus
RXSTPI
RXOUTI
TXINI
Wr Enable
HOST
Wr Enable
CPU
SETUP
SETUP
HW
IN
SW
SW
HW
DATA
IN
SW
STATUS
OUT
NAK
OUT
HW
SW
A NAK handshake is always generated as the first status stage command. The UESTAn.NAKINI
bit is set. It allows the user to know that the host aborts the IN data stage. As a consequence,
the user should stop processing the IN data stage and should prepare to receive the OUT status
stage by checking the UESTAn.RXOUTI bit.
The OUT retry is always ACKed. This OUT reception sets RXOUTI. Handle this with the follow-
ing software algorithm:
// process the IN data stage
set TXINI
wait for RXOUTI (rising) OR TXINI (falling)
if RXOUTI is high, then process the OUT status stage
if TXINI is low, then return to process the IN data stage
Once the OUT status stage has been received, the USBC waits for a SETUP request. The
SETUP request has priority over all other requests and will be ACKed.
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